1.Design of Area Efficient, High Speed 16-bit Borrow Select Subtractor
Md. IrfazAhmad,R. Ranjith Kumar
PBR Visvodaya Institute of Technology and Science, Kavali, AP, India.
Page No : 1-5
DOI:16.10089.CEJ.2022.V13I10.285311 505
2.Design of high speed 16-bit Fixed-Width Booth Multipliers Using Data Scaling Technology
Thadiparthy Hepsiba Rani,C.V Kavya Suvarchala
PBR Visvodaya Institute of Technology and Science, Kavali, AP, India
Page No : 6-13
DOI:16.10089.CEJ.2022.V13I10.285311 506
3.Defense-in-depth network perimeter security Department of Information Technology
Avinash Singh, Dr Vineet Kumar Singh, Er Paritosh Tripathi
Dr RMLAU Ayodhya, Up
Page No : 14-25
DOI:16.10089.CEJ.2022.V13I10.285311 507